Sensors based on metallic nanowires, nanorods and nanoparticles are increasingly being investigated because of unique electronic, optical, biological and magnetic sensing properties that these nanostructures offer. These properties aid in the development of reliable, improved and fast detection techniques for sensors. Templated synthesis of these nanostructures through plating techniques is increasingly being accepted as an elegant alternative to sophisticated methods such as molecular beam epitaxy and e-beam lithography. The advantages of the template method as known in the art are: (a) batch fabrication ability (b) accurate control of the diameter of the pores through controlled pore growth, (c) control of the pore morphology and (d) control of composition through plating solutions.
It is generally known in the art to synthesize nanowires using electroplating, which is generally done by plating the desired material within cylindrical or monodispersed pores in nanoporous templates. Materials known in the art for use as nanoporous templates include alumite membranes (anodized aluminum films) or track-etched polymer membranes (polycarbonate) or mesoporous silica. Also known in the art is deep reactive ion etching (DRIE) of silicon to realize vertical interconnects. These methods of nanowire synthesis as known in the art have provided nanowires and through-wafer vertical interconnects with aspect ratios (height:width) at a maximum of 10:1. However, higher aspect ratios are required to realize the high-density circuits useful in MEMS/NEMS devices.
Advancements in the field of System-On-Chip (SoC) and 3-D integrated circuits demands an efficient and optimized interconnect scheme. Stray effects are minimized when the electronic circuitry is in close proximity to the transducer. Designing an interconnect scheme to obtain high a fill factor and low loss calls for a vertical interconnect strategy. As devices continue to be scaled down, the contact pad area also shrinks requiring further reductions in the interconnect dimensions.
Synthesized nanowires are used to provide improved packaging and interconnect schemes for integrated circuits and sensors. In particular, the fabrication of through-wafer nanowires to provide vertical interconnects in 3D devices provides for the realization of high-density circuits and systems. High-density arrays of vertical interconnects are of great interest in MEMS/NEMS packaging.
In addition to the use of nanowires for packaging, a major impediment in using nanowires for field deployable systems has been the difficulty inherent in handling the nanowires and functionalization of the sensing elements with nanowires. Fundamentally, fabricating sensing nanowires is a two-step process where (1) the nanowires are bound to the transductor surface and (2) the nanowires are functionalized for the target of interest. These steps may be performed in any order and non-specific binding of wires to targets is a major issue of concern in this process.
Accordingly, what is needed in the art is an improved method for the synthesis and assembly of ultra-high aspect ratio metallic nanowires to be deployed as interconnects and sensing elements thereby providing a generic, high density, reconfigurable and low cost alternative to conventional packaging schemes.